1. Field of the Invention
The present invention relates to a semiconductor device provided with a plurality of field-effect transistors on a semiconductor substrate and a production process thereof.
2. Description of Related Art
A metal oxide semiconductor field-effect transistor (MOSFET) or a metal insulator semiconductor field-effect transistor (MISFET), which has a semiconductor substrate of silicon and a polycrystalline silicon gate, has been developed to have higher performance by various techniques for microfabrication, film-making and impurity controlling. For example, combining MISFETs of different threshold voltage characteristics realizes integrated circuit devices exhibiting various functions.
It is known, however, that carriers are depleted in a gate electrode of polycrystalline silicon, when an MOSFET channel is turned around to deteriorate its performance. Some approaches proposed to avoid the above problem are use of a gate electrode of a metal, metal silicide as a compound of metal and silicon, and metal germanide as a compound of metal and germanium (Patent Document 1, and Non-Patent Documents 1 and 2). FIG. 5 illustrates an MOSFET with a gate electrode of metal silicide 506, as Conventional Example 1, described in Patent Document 1. It has a source-drain region disposed on semiconductor substrate 501 via a channel region. The source-drain region has a structure with lightly doped drains (LDD) or source-drain extensions 502, and a low impurity concentration diffusion region near the channel region. It also has metal silicide films 504 on a high impurity concentration region 503 surface adjacent to the low impurity concentration diffusion region. Semiconductor substrate 501 is an N-type or P-type silicon substrate, or a P-type or N-type well region formed on an N-type or P-type substrate. The gate electrode is formed on gate-insulating film 505. This gate electrode is composed only of metal silicide 506. Each of side spacers 507 for the gate electrode has a structure necessary for forming the source-drain region, and is formed of a silicon oxide or silicon nitride film. The MOSFET as the conventional device (Conventional Example 1) has the gate electrode composed only of metal silicide, and can solve the above-described problem of depletion of the gate electrode. The gate-insulating film may be of silicon oxide or silicon oxynitride, which contains nitrogen. Conventional Example 1 uses cobalt silicide (CoSi2) or NiSi as the metal silicide.
FIG. 6 illustrates a MISFET as Conventional Example 1 production process. First, an isolation film is formed on P- or N-type silicon substrate 601 (FIG. 6A). The isolation film can be formed by shallow trench isolation, for example. A well impurity is injected into an active device by ion implantation. Then, a gate-insulating film and polycrystalline silicon are deposited to 1 to 5 nm and about 50 nm, respectively. Then, the polycrystalline silicon is treated by lithography and anisotropic etching to selectively leave a portion, which later becomes a gate electrode. The gate electrode of polycrystalline silicon is referred to as sacrificial gate 602 (FIG. 6B).
Next, side walls of silicon oxide film 603 are formed by an oxidation step, and source-drain extensions 604 (low impurity concentration regions) are formed by ion implantation (FIG. 6C). They are treated by activation RTA (rapid thermal annealing) carried out at about 800° C., and then by CVD and anisotropic etching to form silicon nitride film spacers 605. Then, high impurity concentration regions 606 in the source-drain regions are formed by ion implantation and activation RTA. High impurity concentration region 606 has a deeper junction than the extension, described above (FIG. 6D).
Then, the polycrystalline silicon film and high impurity concentration regions 606 are coated with a two-layer laminate composed of Co and TiN formed by sputtering in this order, after they are treated to remove the silicon oxide and insulating films from their surfaces. Thickness of the Co film is set at a level necessary for totally converting the polycrystalline silicon into the silicide. In Conventional Example 1, the thickness is set at 16 nm. The TiN film functions as an oxidation inhibiting film (FIG. 6E). The polycrystalline silicon is converted by RTA into CoSi2, which covers high impurity concentration regions 606 in the source-drain regions. Then, the unreacted Co and TiN are removed by selective etching (FIG. 6F).
The subsequent steps (not shown) follow a common procedure for producing an MISFET, involving, for example, deposition of an insulating film to totally cover the above structure, CMP treatment for flattening the film, opening the contact in each of the source, drain and gate regions, and filling the openings with a plug containing tungsten (W) or the like, to produce an MISFET.
This production process gives the gate electrode composed only of the CoSi2 film on the gate-insulating film and, at the same time, a self-aligning silicide electrode structure having a CoSi2 film also in the source-drain regions. It has an advantage for giving a metallic gate electrode by the exactly same number of steps as in a conventional silicide production process.
The production process of Conventional Example 1, however, needs a deeper junction in the high impurity concentration region in the source-drain region than the thickness of CoSi2. It is however necessary to reduce the junction depth of the high impurity concentration region to produce a finer device, and hence to reduce the thickness of the CoSi2 film and also thickness of the polycrystalline silicon film. This causes a problem of reduced margin of the process including the fabrication step.
One of the processes proposed to solve the above problem is the one described in Non-patent Document 3, the process being referred to as Conventional Example 2, which is described by referring to FIG. 7.
Conventional Example 2 adopts a procedure similar to that of Conventional Example 1 for forming a polycrystalline silicon film (FIG. 7A), where gate-insulating film 702 and polycrystalline silicon film 703 are formed on silicon substrate 701 in this order. Then, a hard mask film of silicon oxide is formed and treated by lithography to form hard mask 704. The polycrystalline silicon is treated by anisotropic etching with hard mask 704 to form sacrificial gate of polycrystalline silicon 705 (FIG. 7B).
Then, drain-source extension 706 (low impurity concentration region), side walls of silicon oxide 707 and spacers 708 of silicon nitride film are formed in a manner similar to that for Conventional Example 1. It is noted that this step should be carried out to leave hard mask 704 on the polycrystalline silicon, when spacers of silicon nitride film 708 are formed by anisotropic etching (FIG. 7C).
Next, high impurity concentration region 709 is formed by ion implantation in the source-drain region, and coated selectively with a metal silicide film by a conventional technique. One example of metal silicides useful here is NiSi. The metal silicide film can be obtained by RTA treatment of Ti and TiN films formed in this order at around 450° C. to remove TiN and surplus Ni. This step forms the metal silicide film on the source-drain region but not on sacrificial gate 705, which is covered by hard mask 704 (FIG. 7D).
A silicon oxide film is deposited as interlayer insulation film 710 thicker than depth of the surface steps evolving as a result of formation of the laminate structure of the polycrystalline silicon and hard mask 704, treated to have the flattened surface by CMP, and etched backed to expose the upper side of the polycrystalline silicon (FIG. 7E). A Ni film is formed, and the polycrystalline silicon is totally converted into NiSi (FIG. 7F).
The above process can independently control thickness of the silicide in the source-drain region and that of silicide in the gate electrode.
The conventional examples to convert the gate electrode into CoSi2 or NiSi are described above. The gate electrode and the source-drain region can be composed of a germanide by replacing the silicon substrate with a germanium substrate and forming a germanium film on the gate-insulating film, as proposed by Non-Patent Document 2. Moreover, it is considered that a gate electrode of germanide can be easily formed on a silicon substrate based on the process concept described in Non-patent Document 2 in consideration of that described in Non-patent Document 3. Still more, platinum silicide is also effective as a silicide, according to Patent Document 4.
Non-patent Document 1 points out that, when MISFETs containing a nickel monosilicide (NiSi) gate electrode having a width or length different from that of the another electrode are integrated on a semiconductor substrate, the production processes described in Patent Document 1 and Non-patent Document 3 involve problems occurring while a sacrificial gate of inadequate length is treated to form a silicide to give a defective sacrificial gate. More specifically, sacrificial gate 801 of insufficient length may have Ni-excessive silicide 803, while sacrificial gate 802 of excessive length may turn into unreacted sacrificial gate 804 containing an insufficient amount of silicide because the silicide cannot be formed to an interface with a gate-insulating film (FIGS. 8A and 8B). Non-patent Document 1 discusses that RTA-treatment of polycrystalline silicon can completely convert it into a silicide to solve the above problems.
FIG. 9 illustrates a conventional production process (Conventional Example 3) described in Non-patent Document 1. First, the production process described by Non-patent Document 3 is used to selectively leave polycrystalline silicon to be converted into silicide, form shorter sacrificial gate 901 and longer sacrificial gate 902, and expose their upper sides (FIG. 9A).
Next, a Ni film is deposited, and reacted with polycrystalline silicon by RTA to have a laminated structure of Si/Ni2Si, where polycrystalline silicon film 903 is left to prevent the Si/Ni2Si structure from coming into contact with a gate-insulating film (FIG. 5 in Non-patent Document 5, or FIG. 9B in this specification). Thickness of the Ni2Si film is set in accordance with quantity of Ni deposited, impurity species present in the polycrystalline silicon, and RTA treatment temperature and time. In particular, the effects of RTA temperature are described in Non-patent Document 1, FIGS. 6 and 7. RTA temperature is preferably 300° C. or lower, which is lower than about 400° C. known as a temperature at which NiSi is formed. The unreacted metal is selectively removed by etching. Then, RTA treatment is again used to diffuse Ni from the Ni2Si layer to the lower Si layer. This converts the metallic gate layer which comes into contact with the gate-insulating film into that of NiSi (FIG. 9C).
This process solves problems of variation of MISFET characteristics resulting from the gates of different lengths. Non-patent Document 1 discusses that Ni3Si can be formed by setting a thickness of the Ni film to be reacted with polycrystalline silicon at 1.7 times of the polycrystalline silicon film thickness, and that Ni3Si has a 0.1 to 0.4 eV higher work function than NiSi. Hence, use of Ni3Si for the gate electrode can decrease a threshold voltage of the P-type MISFET.
Non-patent Document 4 discusses a process for forming a silicide gate electrode of Ni-rich composition on a wafer, where the composition contains Ni (including that in NiSi) in excess of Si. This gives the NiSi electrode having a work function of about 4.5 eV and the Ni-rich electrode having a higher work function. The process of Non-Patent Document 4 varies thickness of the polycrystalline silicon to be reacted with Ni between an nMOSFET and a pMOSFET, as does the process described in Non-patent Document 1. It uses a thinner polycrystalline silicon in a P-MOSFET than in an nMOSFET to form NiSi in the nMOSFET and Ni-rich silicide in the pMOSFET. This process, however, involves the reactions of Ni varying with transistor deposition density and Ni-silicon reaction time to vary the Ni/Si ratio. The resulting device can be no longer expected to work properly because of variation of transistor threshold voltage.
There are other attempts made to control the threshold value. Patent Document 2 described a two-layered gate electrode film, with the lower film of silicon doped with an electroconducting material and the upper electroconductive film of metal silicide, wherein thickness of the lower film is varied to control the threshold value. The process, however, involves problems related to gate electrode fabricability. The lower electroconductive film has a varying thickness between n- and p-channel regions although the upper electroconductive film has a constant thickness, with the result that the gate-insulating film or substrate for the thinner electroconductive film will be exposed during an etching step and excessively etched. Moreover, the lower electroconductive film is fabricated in such a way to have the thickness varying between an n- and p-channel transistors, and a silicon oxide film may be partly formed in a layer which is to serve as a gate electrode, making it difficult to carry out etching for gate electrode formation.
Patent Document 3 describes a process for forming gate electrodes composed of a fully silicided and partly silicided portions to control the threshold value by utilizing their different characteristics. However, it still involves problems of gate depletion in the partly silicided gate.    [Patent Document 1] Japanese Patent Laid-Open No. 2000-252462    [Patent Document 2] Japanese Patent Laid-Open No. 2000-243853    [Patent Document 3] Japanese Patent Laid-Open No. 2005-228868    [Patent Document 4] Japanese Patent Laid-Open No. 2005-217275    [Non-Patent Document 1] “Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate length,” 2005 Symposium on VLSI Technology Digest of Technical papers, p. 72-73    [Non-Patent Document 2] “Material Characterization of Metal-Germanide Gate Electrodes Formed by FUGE (Fully Germanided) Process,” Extended Abstract of the 2005 International Conference on Solid State Devices and Materials, Kobe, 2005, p. 844-845    [Non-Patent Document 3] “Demonstration of Fully Ni-Silicided Metal Gates on Hf02 based high-k gate dielectrics as a candidate for low power applications,” 2004 Symposium on VLSI Technology Digest of Technical papers, p. 190-191    [Non-Patent Document 4] “CMOS Integration of Dual Work Function Phase Controlled Ni FUSI with Simultaneous Silicidation of NMOS (NiSi) and PMOS (Ni-rich Silicide) Gates on HfSiON,” Technical Digest of 2005 International Electron Device Meeting, p. 661-664
It is necessary to set different threshold voltages of MISFETs constituting circuits for an LSI, which generally has integrated circuits of various functions. It is known that different threshold voltages can be realized by varying gate-insulating film thickness or channel impurity concentration in MISFETs. By combining with the process described in Non-patent Document 1, these processes can realize different threshold voltages.
However, a number of lithography steps and additional fabrication works are needed for realizing gate-insulating films of varying thicknesses. Moreover, it is difficult for the process described in Non-patent Document 1, which uses nitrided hafnium silicate (HfSiON) for a gate-insulating film, to form gate-insulating films of varying thicknesses on a single substrate.
A threshold voltage can be also controlled by varying impurity concentration in a substrate channel region. Increasing the concentration to increase the threshold voltage, however, may cause problems of deteriorated charge transfer in the channel by a scattered impurity. Decreasing the concentration to decrease the threshold voltage, on the other hand, may cause problems that an MISFET of short gate length can no longer work properly due to the short-channel effect.
Non-patent Document 4 discusses that a metal-rich silicide of monosilicide and metal, which contains the metal in excess of Si, can be produced. However, the reactions of Ni vary with transistor deposition density and Ni-silicon reaction time to vary the Ni/Si composition ratio, as discussed by Non-patent Document 1. The resulting device may be no longer expected to work properly because of variation of the Ni-rich silicide composition and hence variation of transistor threshold voltage.
The present invention has been developed under these situations. It is intended to set different threshold voltages for a semiconductor integrated circuit device which includes metal-insulator semiconductor field-effect transistors with a gate electrode of a metal semiconductor compound containing a metal, silicon and/or germanium as essential components without controlling impurity concentration in a gate-insulating film or channel region.